1. Field of the Invention
The present invention relates generally to a method for optimizing an integrated circuit layout design, and more specifically to a method for optimizing an integrated circuit layout design by separating single holes and redundant holes of line-end holes.
2. Description of the Prior Art
An integrated circuit (IC) is a device, such as a semiconductor device, or an electronic system that includes many electronic components, such as transistors, resistors and diodes. These components are often interconnected to form multiple circuit components, e.g. gates, cells, memory units, arithmetic units, controllers and decoders. An IC includes multiple layers of wiring that interconnects the electronic and circuit components. Design engineers design ICs by transforming logical or circuit descriptions of the components into geometric descriptions, which are called design layouts.
Fabrication foundries (fabs) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e. a photomask) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries (features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring and via pads, as well as other elements that are not functional circuit elements, but are used to facilitate, enhance or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with different conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.